Santa Clara University

IEEE - IEEE


Santa Clara University

and the

Santa Clara Valley Electron Devices Society

Present

IEEE Electron Devices Society Mini-Colloquium
on
Next Generation Device Technologies


Friday, February 23rd
Parlors and Williman Room, Benson Memorial Center





Seating and Parking are LIMITED TO 100!
There are still slots available.
Please register by sending your name and association to eds.ieee@gmail.com

Time

Topic

Speaker


9:30 AM


Registration




9:45 AM



Welcome and Introduction


Prof. C. Yang
and Dr. P. Jansen

10:00 AM

Strain Engineering and Device Performance: Benefit or Compromise?

Prof. Cor Claeys

IMEC, Belgium

10:50 AM

Robust Electrostatic Discharge (ESD) Protection in CMOS Technology

Prof. Juin J. Liou

University of Central Florida

11:40 AM

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

Dr. T. Krishnamohan

Intel

12:30 PM

Lunch and Student Poster Presentation

Dr. S. Saha and Dr. P. Jansen

1:50 PM

RCL Characterization and Modeling of X Architecture Diagonal Wires for VLSI Design

Dr. N.D. Arora

Cadence Design Systems

2:40 PM

Recent Advances in Photonic Devices for RF/Wireless Communication Applications

Prof. Paul K. L. Yu

UC San Diego

3:30 PM

Coffee Break


3:45 PM

FinFET Technology for Nanoscale CMOS Digital Integrated Circuits

Prof. Tsu-Jae King Liu

UC Berkeley





Sponsored by IEEE Electron Devices Society

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