Santa Clara University

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

Dr. T. Krishnamohan,

Intel Corp.

Abstract: Diminishing improvement in the on current (ION) and increase in off current (IOFF) may limit the scaling of bulk Si CMOS. Various techniques like ultra-thin gate dielectrics, shallow source/drain junctions and high channel doping are used to mitigate the short channel effects and improve the device performance. Most of these approaches however directly conflict with the goal of obtaining high carrier mobility, low subthreshold swing, low series resistance, and therefore large ION and low IOFF at low supply voltage. A channel material with high µ and therefore high injection velocity can increase ION and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future scaling of nanoscale MOSFETs it becomes important to look at higher mobility materials, like Ge, strained-SiGe, strained-Ge, and III-V materials like GaAs, InAs, InSb and InGaAs together with innovative device structures which may perform better than even very highly strained Si.

Heterogeneous integration of the high mobility Ge and III-V materials on Si with novel device structures can take us to sub-20 nm regime. Ge will be suitable to satisfy the p-MOS requirements, however, there appear to be severe limitations of n-MOS. High electron mobility III-V materials could be suitable for n-MOS. For both Ge and III-V devices problems of leakage need to be solved. Novel heterostructures will be needed to exploit the promise advantages of Ge and III-V based devices.

Biography: Prof. (Dr.) Tejas Krishnamohan is currently working at Intel Corporation, Santa Clara, USA, and also holds a Consulting Professor position in the Department of Electrical Engineering at Stanford University, CA USA.

He received the B.Tech. degree in 2000 from the Indian Institute of Technology (Mumbai), India, and the M.S. and Ph.D. degrees in 2006 from Stanford University, CA, USA, all in Electrical Engineering.

In 2006, he was a visiting scientist working on high-mobility channel materials at Inter-university Micro-Electronics Center (IMEC), Leuven, Belgium. From 2001-2005 he worked with the Strategic Technology Group at Advanced Micro Devices, CA, USA. He has co-authored over 40 publications and has been the recipient of several best paper awards. Dr. Krishnamohan has worked on physics, technology and modeling of advanced/novel devices for logic and memory, ultra-thin body SOI, double-gate/multi-gate MOSFETs, strained silicon, high-k dielectrics/metal gate, strained germanium MOSFETs, high-mobility channel materials, band-to-band tunneling FETs, carbon nanotube FETs, organic semiconductors and novel non-volatile memory devices.

His research interests are exploring the physics, materials and technology of novel, nanoscale devices for logic and memory applications.