Santa Clara University

RCL Characterization and Modeling of X Architecture Diagonal Wires for VLSI Design

Narain D. Arora,

Cadence Design Systems,

555 River Oaks Parkway, San Jose, CA, 95135

Abstract:The X Architecture diagonal wires that enables IC chip to be faster and smaller, compared to the same design in Manhattan routing, are fabricated using sub 100nm copper CMOS process. This presentation reports the results on RCL characterization, modeling, SEM/FIB analysis of these diagonal lines for VLSI design.

Biography:Dr. Narain D. Arora, Ph.D. (IIT, Delhi), Fellow IEEE, is the Vice President of R&D at Cadence Design Systems. Prior to that he was Vice President and Chief Scientist at Simplex Solutions (1996-2002). Before joining Simplex, he held several engineering and management positions within DEC's semiconductor division over a period of 14-years. The most recent being consulting engineer and manager of DEC's device and interconnect modeling group. Before joining DEC in 1983 he was Post Doctoral Fellow at University of Waterloo, Canada and visiting Professor at NCSU, Raleigh, USA. During 1967-1979 he was Senior Scientific Officer at Defense R&D Labs (ARDE and SSPL). His field of interest is semiconductor process/device design and modeling/characterization including VLSI device/circuit reliability simulation and parasitic (interconnect) modeling and extraction. He has given various invited talks and published over 60 journal papers, has 3 patents to his credit and authored a book "MOSFET Modeling for VLSI Circuit Simulation: Theory and Practice", pp. 596. Springer-Verlag, NY 1993. In 1999, the book was translated to Chinese language and is being reprinted by World Scientific Publications. Dr. Arora is a Distinguished Lecturer of IEEE Electron Devices Society, the founding chair of IEEE Compact Modeling Technical Committee and receipt of two best paper awards.