Santa Clara University

FinFET Technology for Nanoscale CMOS Digital Integrated Circuits

Tsu-Jae King Liu

Electrical Engineering and Computer Sciences

University of California, Berkeley

Abstract: Suppression of leakage current and reduction in device-to-device variability will be key challenges for sub-45nm CMOS technologies.  Non-classical transistor structures such as the FinFET will likely be necessary to meet transistor performance requirements in the sub-20nm gate length regime.  This talk will provide an overview of FinFET technology and describe how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs.

Biography:Professor Tsu-Jae King Liu received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University.  She joined the Xerox Palo Alto Research Center as a Member of Research Staff in 1992, to research and develop polycrystalline-silicon thin-film transistor technologies for flat-panel display applications.   In August 1996 she joined the faculty of the University of California at Berkeley, where she is now Professor of Electrical Engineering and Computer Sciences (EECS) and Director of the UC Berkeley Microfabrication Laboratory.  Her research activities are presently in nanoscale silicon devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics.   She has authored or co-authored over 300 publications and patents, and is an IEEE Fellow.