Quoc Ngo earned his B.S. in Electrical Engineering from Oregon State University in 2001 and his M.S. from Santa Clara University in Electrical Engineering in 2003. He is currently pursuing the Ph.D. degree in Electrical Engineering at Santa Clara University. His primary research interest includes synthesis and modeling of carbon nanotube on-chip interconnects. He is also involved in developing a compact model for MOSFET gate-current. His summer internships at Intel Corporation from 1997-2002 have included Yield Analysis, Defect Metrology, Back-end Integration, and Interconnect Research and Development for developmental 300mm processes. Currently he is actively collaborating with the Center for Nanotechnology, NASA Ames Research Center in an initiative to incorporate carbon nanotubes into silicon-based technology.