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Fr. Dat Tran, S. J.

Biography

Fr. Dat Tran, S. J. is an assistant professor of Electrical and Computer Engineering. He joined the Santa Clara University faculty in September 2020. He received B.S. and M.S. degrees in Electrical Engineering from Portland State University, Portland, OR in 1994 and 1996. From 1996 to 1999, he worked for Tektronix, Inc., as a software design engineer. In 1999, he entered the Society of Jesus, went through the Jesuit formation, and received an M.Div. degree at Jesuit School Theology at Santa Clara in 2009. In 2014, he returned to Portland State University, Portland, OR for a graduate study and received a Ph.D. degree in Electrical Engineering in 2019.

Education

  • Ph.D., Portland State University, Portland, OR, USA, 2019.
  • MDiv., Jesuit School of Theology at Santa Clara, Berkely, CA, USA, 2009.
  • M.S., Portland State University, Portland, OR, USA, 1996.
  • B.S., Portland State University, Portland, OR, USA, 1994.

Courses Taught

  • ELEN 20 - Emerging Areas in Electrical and Computer Engineering
  • ELEN 21 - Introduction to Logic Design
  • ELEN 21L - Introduction to Logic Design Lab
  • ELEN 50 - Electric Circuits 1
  • ELEN 50L - Electric Circuit 1 Lab

Research

Current multicore architectures and devices inevitably reach their physical limitations. Biological computing is an alternative architecture that offers non-traditional computing systems. His research focuses on different neuromorphic computing architectures using emergent nanodevices as computing platforms.

Publications

  1. Tran, SJ Dat, and Christof Teuscher. "Computational Capacity of Complex Memcapacitive Networks." ACM Journal on Emerging Technologies in Computing Systems (JETC) 17.2 (2021): 1-25.Link
  2. Tran, SJ Dat, and Christof Teuscher. "Deep Memcapacitive Network." 2020 IEEE 15th International Conference on Nano/Micro Engineered and Molecular System (NEMS). IEEE, 2020.Link
  3. Tran, SJ Dat, and Christof Teuscher. "Hierarchical Memcapacitive Reservoir Computing Architecture." 2019 IEEE International Conference on Rebooting Computing (ICRC). IEEE, 2019.Link
  4. Tran, SJ Dat, and Christof Teuscher. "Memcapacitive reservoir computing." 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, 2017.Link
  5. Tran, SJ Dat, and Christof Teuscher. "Memcapacitive Devices in Logic and Crossbar Applications." International Journal of Unconventional Computing 13.1 (2017).Link
  6. Woods, W., Taha, M.M.A., Tran, S.J., Bürger, J. and Teuscher, C., 2015, July. Memristor panic—A survey of different device models in crossbar architectures. In Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´ 15) (pp. 106-111). IEEE.Link

Dissertation

  1. Tran, S.J. Dat, “Memcapacitive Reservoir Computing Architectures,” Ph.D. Dissertation, Department of Electrical and Computer Engineering, Portland State University, June 2019. Link